In devices for trunk communication and information processing devices such as servers, a high-speed I/O circuit is used to transmit and receive a signal at a high bit rate within an integrated circuit chip used in the devices and between integrated circuit chips (within the device and between the devices).
A related technology is disclosed in Japanese Laid-open Patent Publication No. 2007-174023.
Other related technologies are disclosed in O. Tyshchenko, A. Sheikholeslami, H. Tamura, M. Kibune, H. Yamaguchi, and J. Ogawa, “A 5 Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 6, pp. 1091-1098, June. 2010, O. Tyshchenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, T. Yamamoto, “A Fractional-Sampling-Rate ADC-Based CDR with Feed-Forward Architecture in 65 nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 166-167, February 2010, Mueller, K. & Muller, M. “Timing Recovery in Digital Synchronous Data Receivers”, IEEE Transactions on Communications, 1976, 24, 516-531, and Spagna, F.; Chen, L.; Deshpande, M.; Fan, Y.; Gambetta, D.; Gowder, S.; Iyer, S.; Kumar, R.; Kwok, P.; Krishnamurthy, R.; chun Lin, C.; Mohanavelu, R.; Nicholson, R.; Ou, J.; Pasquarella, M.; Prasad, K.; Rustam, H.; Tong, L.; Tran, A.; Wu, J. & Zhang, X. “A 78 mW 11.8 Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32 nm CMOS”, IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 2010, 366-367.